mirror of
git://repo.or.cz/tinycc.git
synced 2026-06-17 15:44:18 +08:00
Implement some RV64F/D instructions
This patch implements some instructions required by musl 1.1.24.
This commit is contained in:
Aleksi Hannula
parent
3c631fdb6d
commit
06e24e7eed
144
riscv64-asm.c
144
riscv64-asm.c
@ -63,6 +63,9 @@ static void asm_emit_opcode(uint32_t opcode);
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static void asm_emit_r(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
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static void asm_emit_s(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
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static void asm_emit_u(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
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static void asm_emit_f(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
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static void asm_emit_fb(int token, uint32_t opcode, const Operand *rd, const Operand *rs);
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static void asm_emit_fq(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2, const Operand *rs3);
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ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, int nb_outputs, int is_output, uint8_t *clobber_regs, int out_reg);
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static void asm_nullary_opcode(TCCState *s1, int token);
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ST_FUNC void asm_opcode(TCCState *s1, int token);
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@ -587,6 +590,14 @@ static void asm_binary_opcode(TCCState* s1, int token)
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asm_emit_css(token, 2 | (5 << 13), ops, ops + 1);
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return;
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/* F/D extension */
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case TOK_ASM_fsqrt_d:
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asm_emit_fb(token, 0x53 | (11 << 27) | (1 << 25) | (7 << 12), ops, ops + 1);
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return;
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case TOK_ASM_fsqrt_s:
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asm_emit_fb(token, 0x53 | (11 << 27) | (0 << 25) | (7 << 12), ops, ops + 1);
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return;
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/* pseudoinstructions */
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/* rd, sym */
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case TOK_ASM_la:
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@ -682,6 +693,15 @@ static void asm_binary_opcode(TCCState* s1, int token)
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asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &zero, &ops[1]);
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return;
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case TOK_ASM_fabs_d:
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/* fsgnjx.d rd, rs, rs */
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asm_emit_f(token, 0x53 | (4 << 27) | (1 << 25) | (2 << 12), &ops[0], &ops[1], &ops[1]);
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return;
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case TOK_ASM_fabs_s:
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/* fsgnjx.s rd, rs, rs */
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asm_emit_f(token, 0x53 | (4 << 27) | (0 << 25) | (2 << 12), &ops[0], &ops[1], &ops[1]);
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return;
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default:
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expect("binary instruction");
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}
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@ -709,6 +729,73 @@ static void asm_emit_r(int token, uint32_t opcode, const Operand* rd, const Oper
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gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg));
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}
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/* caller: Add rounding mode, fmt, funct5 to opcode */
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static void asm_emit_f(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
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{
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if (rd->type != OP_REG || !REG_IS_FLOAT(rd->reg)) {
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tcc_error("'%s': Expected destination operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs1->type != OP_REG || !REG_IS_FLOAT(rs1->reg)) {
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tcc_error("'%s': Expected first source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs2->type != OP_REG || !REG_IS_FLOAT(rs2->reg)) {
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tcc_error("'%s': Expected second source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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/* F-type instruction:
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31...27 funct5
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26...25 fmt
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24...20 rs2
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19...15 rs1
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14...12 rm
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11...7 rd
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6...0 opcode = OP-FP */
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gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg));
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}
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/* caller: Add rounding mode, fmt, funct5 to opcode */
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static void asm_emit_fb(int token, uint32_t opcode, const Operand* rd, const Operand* rs)
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{
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if (rd->type != OP_REG || !REG_IS_FLOAT(rd->reg)) {
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tcc_error("'%s': Expected destination operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs->type != OP_REG || !REG_IS_FLOAT(rs->reg)) {
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tcc_error("'%s': Expected source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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/* F-type instruction:
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31...27 funct5
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26...25 fmt
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24...20 rs2 = 0
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19...15 rs1 = rs
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14...12 rm
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11...7 rd
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6...0 opcode = OP-FP */
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gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs->reg) | ENCODE_RS2(0));
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}
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/* caller: Add rounding mode, fmt to opcode */
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static void asm_emit_fq(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2, const Operand* rs3)
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{
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if (rd->type != OP_REG || !REG_IS_FLOAT(rd->reg)) {
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tcc_error("'%s': Expected destination operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs1->type != OP_REG || !REG_IS_FLOAT(rs1->reg)) {
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tcc_error("'%s': Expected first source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs2->type != OP_REG || !REG_IS_FLOAT(rs2->reg)) {
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tcc_error("'%s': Expected second source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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if (rs3->type != OP_REG || !REG_IS_FLOAT(rs3->reg)) {
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tcc_error("'%s': Expected third source operand that is a floating-point register", get_tok_str(token, NULL));
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}
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/* F-type instruction:
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31...27 rs3
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26...25 fmt
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24...20 rs2
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19...15 rs1
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14...12 rm
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11...7 rd
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6...0 opcode */
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gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | (REG_VALUE(rs3->reg) << 27));
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}
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/* caller: Add funct3 into opcode */
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static void asm_emit_i(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
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{
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@ -1089,11 +1176,49 @@ static void asm_ternary_opcode(TCCState *s1, int token)
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asm_emit_cs(token, 6 << 13, ops, ops + 1, ops + 2);
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return;
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/* F/D extension */
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case TOK_ASM_fsgnj_d:
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asm_emit_f(token, 0x53 | (4 << 27) | (1 << 25) | (0 << 12), ops, ops + 1, ops + 2);
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return;
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case TOK_ASM_fsgnj_s:
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asm_emit_f(token, 0x53 | (4 << 27) | (0 << 25) | (0 << 12), ops, ops + 1, ops + 2);
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return;
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case TOK_ASM_fmax_d:
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asm_emit_f(token, 0x53 | (5 << 27) | (1 << 25) | (1 << 12), ops, ops + 1, ops + 2);
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return;
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case TOK_ASM_fmax_s:
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asm_emit_f(token, 0x53 | (5 << 27) | (0 << 25) | (1 << 12), ops, ops + 1, ops + 2);
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return;
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case TOK_ASM_fmin_d:
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asm_emit_f(token, 0x53 | (5 << 27) | (1 << 25) | (0 << 12), ops, ops + 1, ops + 2);
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return;
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case TOK_ASM_fmin_s:
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asm_emit_f(token, 0x53 | (5 << 27) | (0 << 25) | (0 << 12), ops, ops + 1, ops + 2);
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return;
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default:
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expect("ternary instruction");
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}
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}
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static void asm_quaternary_opcode(TCCState *s1, int token)
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{
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Operand ops[4];
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parse_operands(s1, &ops[0], 4);
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switch (token) {
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case TOK_ASM_fmadd_d:
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asm_emit_fq(token, 0x43 | (1 << 25) | (7 << 12), ops, ops + 1, ops + 2, ops + 3);
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return;
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case TOK_ASM_fmadd_s:
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asm_emit_fq(token, 0x43 | (0 << 25) | (7 << 12), ops, ops + 1, ops + 2, ops + 3);
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return;
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default:
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expect("quaternary instruction");
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}
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}
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static void asm_atomic_opcode(TCCState *s1, int token)
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{
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Operand ops[3];
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@ -1271,6 +1396,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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case TOK_ASM_lui:
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case TOK_ASM_auipc:
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case TOK_ASM_fsqrt_s:
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case TOK_ASM_fsqrt_d:
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asm_binary_opcode(s1, token);
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return;
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@ -1349,8 +1476,19 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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case TOK_ASM_csrrsi:
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case TOK_ASM_csrrw:
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case TOK_ASM_csrrwi:
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/* F/D extension */
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case TOK_ASM_fsgnj_d:
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case TOK_ASM_fsgnj_s:
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case TOK_ASM_fmax_s:
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case TOK_ASM_fmax_d:
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case TOK_ASM_fmin_s:
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case TOK_ASM_fmin_d:
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asm_ternary_opcode(s1, token);
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return;
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case TOK_ASM_fmadd_d:
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case TOK_ASM_fmadd_s:
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asm_quaternary_opcode(s1, token);
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return;
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/* Branches */
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case TOK_ASM_beq:
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@ -1441,6 +1579,8 @@ ST_FUNC void asm_opcode(TCCState *s1, int token)
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case TOK_ASM_not:
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case TOK_ASM_neg:
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case TOK_ASM_negw:
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case TOK_ASM_fabs_s:
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case TOK_ASM_fabs_d:
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asm_binary_opcode(s1, token);
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return;
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@ -1556,7 +1696,7 @@ ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier)
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if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
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(sv->type.t & VT_BTYPE) == VT_DOUBLE) {
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/* floating point register */
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reg = TOK_ASM_f0 + reg;
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reg = TOK_ASM_f0 + REG_VALUE(reg);
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} else {
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/* general purpose register */
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reg = TOK_ASM_x0 + reg;
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@ -1570,7 +1710,7 @@ ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier)
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if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
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(sv->type.t & VT_BTYPE) == VT_DOUBLE) {
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/* floating point register */
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reg = TOK_ASM_f0 + reg;
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reg = TOK_ASM_f0 + REG_VALUE(reg);
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} else {
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/* general purpose register */
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reg = TOK_ASM_x0 + reg;
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@ -266,6 +266,19 @@
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DEF_ASM(remw)
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DEF_ASM(remuw)
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/* "F"/"D" Extension for Single/Double-Precision Floating Point Arithmetic, V2.2 */
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/* enough implemented for musl */
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DEF_ASM_WITH_SUFFIX(fsgnj, s)
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DEF_ASM_WITH_SUFFIX(fsgnj, d)
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DEF_ASM_WITH_SUFFIX(fmadd, s)
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DEF_ASM_WITH_SUFFIX(fmadd, d)
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DEF_ASM_WITH_SUFFIX(fmax, s)
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DEF_ASM_WITH_SUFFIX(fmax, d)
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DEF_ASM_WITH_SUFFIX(fmin, s)
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DEF_ASM_WITH_SUFFIX(fmin, d)
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DEF_ASM_WITH_SUFFIX(fsqrt, s)
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DEF_ASM_WITH_SUFFIX(fsqrt, d)
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/* "C" Extension for Compressed Instructions, V2.0 */
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DEF_ASM_WITH_SUFFIX(c, nop)
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/* Loads */
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