From 5f179d68851de7ae1eff80602b99438c84de6061 Mon Sep 17 00:00:00 2001 From: Benjamin Oldenburg Date: Sat, 21 Mar 2026 02:13:20 +0700 Subject: [PATCH] docs: add lesson learned - arm64 asm test widths --- .docs/lessons_learned.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.docs/lessons_learned.md b/.docs/lessons_learned.md index b3de15ff..1ab0dfc1 100644 --- a/.docs/lessons_learned.md +++ b/.docs/lessons_learned.md @@ -4,3 +4,10 @@ Root Cause: The inline asm layer mixed architectural register numbers with arm64 Solution: Keep assembler parsing on architectural register numbers, but allocate inline asm operands and clobbers using the backend's internal FP register range. Implement official AArch64 operand modifiers in `tccasm.c`/`arm64-asm.c`, fix STP/LDP/STR/LDR save/restore emission to use `SP` as base and restore the full stack adjustment, and fix register-shift plus `ROR` immediate/register alias handling. Prevention: When touching ARM64 inline asm, verify both the Arm ISA docs and the backend register model in `arm64-gen.c`. Do not assume architectural register numbers match allocator register numbers, and validate changes with small object-compilation snippets plus disassembly before trying full runtime tests. Related Files: [arm64-asm.c, arm64-gen.c, tccasm.c, tests/asm/test-asm-arm64-ext.c, tests/asm/test-asm-arm64-ext-fixed.c] + +Date: 2026-03-21 +Problem: The ARM64 inline-asm test executables still segfaulted after all tests printed as passed. +Root Cause: Two tests used generic `%0`/`%1` register substitution for `ldr`/`str` on 32-bit `int` variables. TCC legitimately chose 64-bit X registers, so the generated memory ops became 64-bit loads/stores and the store test overwrote the saved frame pointer in its stack frame. +Solution: Update the tests to use `%w0`/`%w1` for 32-bit load/store instructions so the emitted code uses `ldr wN`/`str wN` and does not trample the stack frame. +Prevention: For AArch64 inline asm tests, always spell the width explicitly on load/store operands when the C type is narrower than 64 bits. Generic `%0` with an `"r"` constraint is not enough to force a W register. +Related Files: [tests/asm/test-asm-arm64-ext.c, tests/asm/test-asm-arm64-ext-fixed.c]