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refactor: replace vector load/store and struct load opcodes with symbolic constants (Phase 2.2)

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arm64-gen.c:
- arm64_ldrv(): ARM64_LDR_SCALAR, ARM64_LDUR_Q_SIMD, ARM64_LDR_Q_REG
- arm64_strx(): ARM64_STR_B, ARM64_STUR_B, ARM64_STR_B_REG
- arm64_strv(): ARM64_STR_SCALAR, ARM64_STUR_Q_SIMD, ARM64_STR_Q_REG
- arm64_ldrs(): ARM64_ORR_REG_LSL, ARM64_LSR_IMM_32, ARM64_LSR_IMM

arm64-tok.h:
- ARM64_LDR_SCALAR (0x3D400000U)
- ARM64_STR_SCALAR (0x3D000000U)
- ARM64_LSR_IMM_32 (0x53000000U)
- ARM64_STR_X_PRE (0xF8000000U)
- ARM64_LDR_X_POST (0xF8400000U)

All 137 tests2 tests pass.
This commit is contained in:
Benjamin Oldenburg 2026-03-21 00:58:48 +07:00
parent 84842db4b2
commit 7d2f376843
2 changed files with 10 additions and 3 deletions
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6
arm64-gen.c
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@ -349,14 +349,14 @@ static void arm64_ldrv(int sz_, int dst, int bas, uint64_t off)
uint64_t scaled_mask = 0xffful << sz;
if (!(off & ~scaled_mask))
o(0x3d400000 | dst | bas << 5 | off << (10 - sz) |
o(ARM64_LDR_SCALAR | dst | bas << 5 | off << (10 - sz) |
(sz & 4) << 21 | (sz & 3) << 30); // ldr (s|d|q)(dst),[x(bas),#(off)]
else if (off < 256 || -off <= 256)
o(0x3c400000 | dst | bas << 5 | (off & 511) << 12 |
o(ARM64_LDUR_Q_SIMD | dst | bas << 5 | (off & 511) << 12 |
(sz & 4) << 21 | (sz & 3) << 30); // ldur (s|d|q)(dst),[x(bas),#(off)]
else {
arm64_movimm(30, off); // use x30 for offset
o(0x3c606800 | dst | bas << 5 | (uint32_t)30 << 16 |
o(ARM64_LDR_Q_REG | dst | bas << 5 | (uint32_t)30 << 16 |
sz << 30 | (sz & 4) << 21); // ldr (s|d|q)(dst),[x(bas),x30]
}
}

7
arm64-tok.h
View File

@ -627,10 +627,16 @@
#define ARM64_STR_B_REG 0x38206800U
#define ARM64_STR_H_REG 0x78206800U
/* Load/store (pre/post-indexed) */
#define ARM64_STR_X_PRE 0xF8000000U /* STR X pre-indexed base */
#define ARM64_LDR_X_POST 0xF8400000U /* LDR X post-indexed base */
/* SIMD load/store (unsigned immediate) */
#define ARM64_LDR_SCALAR 0x3D400000U /* Base for scalar load (size built dynamically) */
#define ARM64_LDR_S_VEC 0xBD400000U
#define ARM64_LDR_D_VEC 0xFD400000U
#define ARM64_LDR_Q_VEC 0x3DC00000U
#define ARM64_STR_SCALAR 0x3D000000U /* Base for scalar store (size built dynamically) */
#define ARM64_STR_S_VEC 0xBD000000U
#define ARM64_STR_D_VEC 0xFD000000U
#define ARM64_STR_Q_VEC 0x3D800000U
@ -696,6 +702,7 @@
/* Shifts (immediate - UBFM/SBFM) */
#define ARM64_LSL_IMM 0xD3400000U
#define ARM64_LSR_IMM 0xD3400000U
#define ARM64_LSR_IMM_32 0x53000000U /* 32-bit LSR base */
#define ARM64_ASR_IMM 0x93400000U
/* Shifted register encoding for ORR/AND/EOR */