From 926f4a3cb8aabc2d71ce4fc3e94c60484735d37d Mon Sep 17 00:00:00 2001 From: Benjamin Oldenburg Date: Fri, 20 Mar 2026 23:16:59 +0700 Subject: [PATCH] feat(arm64): add more opcode constants for code generator Add additional ARM64 instruction opcode constants needed by arm64-gen.c: - ARM64_FMOV_*: Floating-point move variants - ARM64_STR_Q_PRE/LDR_Q_POST: Quadword load/store with pre/post increment - ARM64_LDPSW: Load pair of words with sign-extend - ARM64_LDR_S_SIMD: SIMD load (distinct from scalar LDR_S) - ARM64_MOV_V_D: Move vector to double - ARM64_FCMP: Floating-point compare - ARM64_SDIV: Signed divide - ARM64_MUL: Multiply These constants will be used in the next commit to refactor arm64-gen.c. --- arm64-tok.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arm64-tok.h b/arm64-tok.h index a7301c54..f73f0b3e 100644 --- a/arm64-tok.h +++ b/arm64-tok.h @@ -703,3 +703,17 @@ #define ARM64_ISB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8) #define ARM64_DSB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8) #define ARM64_DMB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8) + +/* Additional opcodes for code generator */ +#define ARM64_FMOV_S_D 0x4EA01C00U +#define ARM64_FMOV_D_S 0x1E604000U +#define ARM64_FMOV_X_D 0x9E660000U +#define ARM64_FMOV_W_S 0x1E260000U +#define ARM64_STR_Q_PRE 0x3C9F0FE0U +#define ARM64_LDR_Q_POST 0x3CC107E0U +#define ARM64_LDPSW 0x4C402BDCU +#define ARM64_LDR_S_SIMD 0x0D00801CU /* SIMD load (different from ARM64_LDR_S) */ +#define ARM64_MOV_V_D 0x4E083C00U +#define ARM64_FCMP 0x1E202008U +#define ARM64_SDIV 0x1AC00C00U +#define ARM64_MUL 0x1B007C00U