From a8cccbabb9cbf3406ec078dcae89fcd0642938c6 Mon Sep 17 00:00:00 2001 From: Benjamin Oldenburg Date: Sat, 21 Mar 2026 02:00:59 +0700 Subject: [PATCH] docs: add lesson learned - arm64 inline asm reg mapping --- .docs/lessons_learned.md | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 .docs/lessons_learned.md diff --git a/.docs/lessons_learned.md b/.docs/lessons_learned.md new file mode 100644 index 00000000..b3de15ff --- /dev/null +++ b/.docs/lessons_learned.md @@ -0,0 +1,6 @@ +Date: 2026-03-21 +Problem: ARM64 extended inline asm support crashed when using FP/SIMD constraints and produced incorrect save/restore and shift encodings. +Root Cause: The inline asm layer mixed architectural register numbers with arm64-gen.c's internal allocator register numbers. FP/SIMD operands were allocated as synthetic 32..63 registers even though the backend only exposes internal FP registers `TREG_F(0..7)`. The save/restore helper also encoded STP/LDP/STR/LDR fields incorrectly, and shift aliases were not implemented according to the A64 instruction definitions. +Solution: Keep assembler parsing on architectural register numbers, but allocate inline asm operands and clobbers using the backend's internal FP register range. Implement official AArch64 operand modifiers in `tccasm.c`/`arm64-asm.c`, fix STP/LDP/STR/LDR save/restore emission to use `SP` as base and restore the full stack adjustment, and fix register-shift plus `ROR` immediate/register alias handling. +Prevention: When touching ARM64 inline asm, verify both the Arm ISA docs and the backend register model in `arm64-gen.c`. Do not assume architectural register numbers match allocator register numbers, and validate changes with small object-compilation snippets plus disassembly before trying full runtime tests. +Related Files: [arm64-asm.c, arm64-gen.c, tccasm.c, tests/asm/test-asm-arm64-ext.c, tests/asm/test-asm-arm64-ext-fixed.c]