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sext.w: addiw rd, rs, 0 (sign-extend 32-bit word) fmv.s/fmv.d: fsgnj.s/d rd, rs, rs (float register move) fneg.s/fneg.d: fsgnjn.s/d rd, rs, rs (float register negate) These were defined in riscv64-tok.h but had no handler code. CSR pseudo-instructions (csrr, csrw, csrci, csrsi, csrwi) skipped for now — they require CSR operand parsing in binary mode.
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2 lines
5 B
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PASS
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