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synced 2026-06-17 15:44:18 +08:00
ff917c09aa
Replaces the empty stub that relied on 'RV64 registers are always sign-extended' assumption. Now emits addiw rd, rs, 0 for proper 32-to-64 bit sign extension, matching arm64's sxtw behavior. Verified on Spacemit X100: tests2 pass (125_atomic_misc has a pre-existing intermittent segfault, not caused by this change).
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
#include <stdio.h>
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/* gen_cvt_sxtw test: verify sign-extension from 32-bit int to 64-bit long long.
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Without the fix, the riscv64 backend had an empty stub for gen_cvt_sxtw,
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leaving upper 32 bits unmodified (containing whatever was in the register
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before), so (long long)(int)x produced wrong results for negative values. */
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int main(void)
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{
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int ok = 1;
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int x = 0x80000000;
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long long y = (long long)x;
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printf("y=%llx\n", (unsigned long long)y);
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if (y != 0xffffffff80000000LL) {
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printf("FAIL: int→long long sign-extension\n");
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ok = 0;
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}
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/* Also test positive value. */
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x = 0x40000000;
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y = (long long)x;
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printf("y=%llx\n", (unsigned long long)y);
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if (y != 0x40000000LL) {
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printf("FAIL: int→long long positive value\n");
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ok = 0;
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}
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/* Test via unsigned int to catch zero-extension vs sign-extension. */
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unsigned int ux = 0x80000000;
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long long uy = (long long)(int)ux;
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printf("uy=%llx\n", (unsigned long long)uy);
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if (uy != 0xffffffff80000000LL) {
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printf("FAIL: unsigned→int→long long sign-extension\n");
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ok = 0;
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}
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printf("%s\n", ok ? "PASS" : "FAIL");
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return ok ? 0 : 1;
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}
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