mirror of
git://repo.or.cz/tinycc.git
synced 2026-06-17 15:44:18 +08:00
ff917c09aa
Replaces the empty stub that relied on 'RV64 registers are always sign-extended' assumption. Now emits addiw rd, rs, 0 for proper 32-to-64 bit sign extension, matching arm64's sxtw behavior. Verified on Spacemit X100: tests2 pass (125_atomic_misc has a pre-existing intermittent segfault, not caused by this change).
5 lines
55 B
Plaintext
5 lines
55 B
Plaintext
y=ffffffff80000000
|
|
y=40000000
|
|
uy=ffffffff80000000
|
|
PASS
|