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273978b927
sext.w: addiw rd, rs, 0 (sign-extend 32-bit word) fmv.s/fmv.d: fsgnj.s/d rd, rs, rs (float register move) fneg.s/fneg.d: fsgnjn.s/d rd, rs, rs (float register negate) These were defined in riscv64-tok.h but had no handler code. CSR pseudo-instructions (csrr, csrw, csrci, csrsi, csrwi) skipped for now — they require CSR operand parsing in binary mode.
101 lines
1.7 KiB
C
101 lines
1.7 KiB
C
#include <stdio.h>
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/* P0.4 + P1.4: riscv64 asm pseudo-instructions test.
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Exercises neg/negw, sext.w, fmv.s/d, fneg.s/d. */
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#ifdef __riscv
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int test_neg(int x)
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{
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int r;
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asm("neg %0, %1" : "=r"(r) : "r"(x));
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return r;
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}
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long long test_negw(long long x)
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{
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int r;
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asm("negw %0, %1" : "=r"(r) : "r"((int)x));
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return (long long)r;
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}
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long long test_sextw(int x)
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{
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long long r;
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asm("sext.w %0, %1" : "=r"(r) : "r"(x));
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return r;
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}
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float test_fmv_s(float a)
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{
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float r;
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asm("fmv.s %0, %1" : "=f"(r) : "f"(a));
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return r;
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}
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float test_fneg_s(float a)
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{
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float r;
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asm("fneg.s %0, %1" : "=f"(r) : "f"(a));
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return r;
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}
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double test_fmv_d(double a)
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{
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double r;
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asm("fmv.d %0, %1" : "=f"(r) : "f"(a));
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return r;
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}
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double test_fneg_d(double a)
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{
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double r;
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asm("fneg.d %0, %1" : "=f"(r) : "f"(a));
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return r;
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}
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int main(void)
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{
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int ok = 1;
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if (test_neg(42) != -42) {
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printf("FAIL: neg\n");
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ok = 0;
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}
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if (test_negw(100) != -100) {
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printf("FAIL: negw\n");
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ok = 0;
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}
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if (test_sextw(0x80000000) != 0xffffffff80000000LL) {
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printf("FAIL: sext.w\n");
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ok = 0;
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}
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if (test_fmv_s(3.14f) != 3.14f) {
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printf("FAIL: fmv.s\n");
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ok = 0;
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}
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if (test_fneg_s(3.14f) != -3.14f) {
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printf("FAIL: fneg.s\n");
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ok = 0;
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}
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if (test_fmv_d(2.718281828) != 2.718281828) {
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printf("FAIL: fmv.d\n");
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ok = 0;
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}
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if (test_fneg_d(2.718281828) != -2.718281828) {
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printf("FAIL: fneg.d\n");
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ok = 0;
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}
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printf("%s\n", ok ? "PASS" : "FAIL");
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return ok ? 0 : 1;
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}
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#else
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int main(void)
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{
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printf("SKIP\n");
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return 0;
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}
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#endif
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