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f8011ea9b7
Add handlers for csrr, csrw, csrwi, csrsi, csrci as pseudo-instructions: csrr rd, csr -> csrrs rd, csr, x0 csrw csr, rs -> csrrw x0, csr, rs csrwi csr, uimm -> csrrwi x0, csr, uimm csrsi csr, uimm -> csrrsi x0, csr, uimm csrci csr, uimm -> csrrci x0, csr, uimm Tokens were already defined in riscv64-tok.h. Tested on Spacemit X100 using fcsr (0x003) which is accessible in user mode. cycle/instret CSRs are privileged and not accessible from Linux user mode on this hardware.
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
#include <stdio.h>
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#ifdef __riscv
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int main(void)
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{
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int ok = 1;
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int old, tmp;
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asm volatile("csrr %0, 0x003" : "=r"(old));
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asm volatile("csrr %0, 0x003" : "=r"(tmp));
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printf("csrr fcsr=%x\n", (unsigned)tmp);
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asm volatile("csrw 0x003, %0" : : "r"(0xE0));
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asm volatile("csrr %0, 0x003" : "=r"(tmp));
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printf("csrw: wrote e0 got %x\n", (unsigned)tmp);
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if (tmp != 0xE0) { printf("FAIL: csrw\n"); ok = 0; }
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asm volatile("csrw 0x003, %0" : : "r"(old));
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asm volatile("csrwi 0x003, 0x10");
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asm volatile("csrr %0, 0x003" : "=r"(tmp));
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printf("csrwi: wrote 0x10 got %x\n", (unsigned)tmp);
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if (tmp != 0x10) { printf("FAIL: csrwi\n"); ok = 0; }
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asm volatile("csrw 0x003, %0" : : "r"(old));
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asm volatile("csrsi 0x003, 0x03");
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asm volatile("csrr %0, 0x003" : "=r"(tmp));
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printf("csrsi: old|3=%x\n", (unsigned)tmp);
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if ((old | 0x03) != tmp) { printf("FAIL: csrsi\n"); ok = 0; }
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asm volatile("csrw 0x003, %0" : : "r"(old));
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asm volatile("csrci 0x003, 0x03");
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asm volatile("csrr %0, 0x003" : "=r"(tmp));
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printf("csrci: old&~3=%x\n", (unsigned)tmp);
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if ((old & ~0x03) != tmp) { printf("FAIL: csrci\n"); ok = 0; }
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asm volatile("csrw 0x003, %0" : : "r"(old));
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printf("%s\n", ok ? "PASS" : "FAIL");
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return ok ? 0 : 1;
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}
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#else
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int main(void)
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{
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printf("SKIP\n");
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return 0;
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}
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#endif
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