tinycc/tests/tests2/144_riscv_csr_pseudo.expect
Meng Zhuo f8011ea9b7 riscv64-asm: implement CSR pseudo-instructions
Add handlers for csrr, csrw, csrwi, csrsi, csrci as pseudo-instructions:
  csrr rd, csr     -> csrrs rd, csr, x0
  csrw csr, rs     -> csrrw x0, csr, rs
  csrwi csr, uimm  -> csrrwi x0, csr, uimm
  csrsi csr, uimm  -> csrrsi x0, csr, uimm
  csrci csr, uimm  -> csrrci x0, csr, uimm

Tokens were already defined in riscv64-tok.h.  Tested on
Spacemit X100 using fcsr (0x003) which is accessible in user mode.
cycle/instret CSRs are privileged and not accessible from Linux
user mode on this hardware.
2026-05-06 18:33:15 +08:00

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