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016087c954
AMO (A-extension):
18 base instructions: amoadd/swap/and/or/xor/max/maxu/min/minu .w/.d
6 aq/rl suffixes: amoadd.w.aq/.rl/.aqrl, amoadd.d.aq/.rl/.aqrl
Correct funct5 (GNU as verified):
amoadd=0x00 amoswap=0x01 amoxor=0x04
amoand=0x0C amoor=0x08 amomax=0x14
amomaxu=0x1C amomin=0x10 amominu=0x18
R-type opcode 0x2F, aq/rl in bits [26:25]
FCVT rounding modes (GNU operand syntax):
fcvt.w.s rd, rs1 [, rtz/rne/rup] -- optional 3rd operand
asm_fcvt_opcode() handler with asm_fcvt_rm() helper
Keywords rne=0, rtz=1, rdn=2, rup=3, rmm=4
FCVT encoding fixes:
fcvt.s.d: funct7 0x40->0x20
fcvt.d.s: funct7 0x42->0x21
Tests: 144 CSR, 145 F/D cmp+cvt, 146 AMO, 147 fcvt round.
All verified against riscv64-linux-gnu-as 2.44 on Spacemit X100.
30 lines
770 B
C
30 lines
770 B
C
#include <stdio.h>
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#ifdef __riscv
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int main(void)
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{
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/* AMO base (all funct5 now match GNU as) */
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asm volatile("amoadd.w a0, a1, (sp)");
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asm volatile("amoswap.w a0, a1, (sp)");
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asm volatile("amoand.w a0, a1, (sp)");
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asm volatile("amoor.d a0, a1, (sp)");
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asm volatile("amoxor.w a0, a1, (sp)");
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asm volatile("amomax.w a0, a1, (sp)");
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asm volatile("amomaxu.d a0, a1, (sp)");
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asm volatile("amomin.w a0, a1, (sp)");
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asm volatile("amominu.d a0, a1, (sp)");
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/* AMO aq/rl ordering suffixes */
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asm volatile("amoadd.w.aq a0, a1, (sp)");
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asm volatile("amoadd.w.rl a0, a1, (sp)");
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asm volatile("amoadd.d.aqrl a0, a1, (sp)");
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printf("PASS\n");
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return 0;
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}
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#else
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int main(void) { printf("SKIP\n"); return 0; }
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#endif
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