mirror of
git://repo.or.cz/tinycc.git
synced 2026-06-17 23:54:16 +08:00
841 lines
19 KiB
C
841 lines
19 KiB
C
/* ------------------------------------------------------------------ */
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/* ARM64 (AArch64) assembler token definitions for TCC */
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/* General purpose registers - 64-bit */
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DEF_ASM(x0)
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DEF_ASM(x1)
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DEF_ASM(x2)
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DEF_ASM(x3)
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DEF_ASM(x4)
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DEF_ASM(x5)
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DEF_ASM(x6)
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DEF_ASM(x7)
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DEF_ASM(x8)
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DEF_ASM(x9)
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DEF_ASM(x10)
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DEF_ASM(x11)
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DEF_ASM(x12)
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DEF_ASM(x13)
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DEF_ASM(x14)
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DEF_ASM(x15)
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DEF_ASM(x16)
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DEF_ASM(x17)
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DEF_ASM(x18)
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DEF_ASM(x19)
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DEF_ASM(x20)
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DEF_ASM(x21)
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DEF_ASM(x22)
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DEF_ASM(x23)
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DEF_ASM(x24)
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DEF_ASM(x25)
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DEF_ASM(x26)
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DEF_ASM(x27)
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DEF_ASM(x28)
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DEF_ASM(x29)
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DEF_ASM(x30)
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/* General purpose registers - 32-bit */
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DEF_ASM(w0)
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DEF_ASM(w1)
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DEF_ASM(w2)
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DEF_ASM(w3)
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DEF_ASM(w4)
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DEF_ASM(w5)
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DEF_ASM(w6)
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DEF_ASM(w7)
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DEF_ASM(w8)
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DEF_ASM(w9)
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DEF_ASM(w10)
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DEF_ASM(w11)
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DEF_ASM(w12)
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DEF_ASM(w13)
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DEF_ASM(w14)
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DEF_ASM(w15)
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DEF_ASM(w16)
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DEF_ASM(w17)
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DEF_ASM(w18)
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DEF_ASM(w19)
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DEF_ASM(w20)
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DEF_ASM(w21)
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DEF_ASM(w22)
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DEF_ASM(w23)
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DEF_ASM(w24)
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DEF_ASM(w25)
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DEF_ASM(w26)
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DEF_ASM(w27)
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DEF_ASM(w28)
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DEF_ASM(w29)
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DEF_ASM(w30)
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/* Special registers */
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DEF_ASM(sp)
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DEF_ASM(xzr)
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DEF_ASM(wzr)
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/* SIMD/FP registers - 128-bit views */
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DEF_ASM(v0)
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DEF_ASM(v1)
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DEF_ASM(v2)
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DEF_ASM(v3)
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DEF_ASM(v4)
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DEF_ASM(v5)
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DEF_ASM(v6)
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DEF_ASM(v7)
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DEF_ASM(v8)
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DEF_ASM(v9)
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DEF_ASM(v10)
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DEF_ASM(v11)
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DEF_ASM(v12)
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DEF_ASM(v13)
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DEF_ASM(v14)
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DEF_ASM(v15)
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DEF_ASM(v16)
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DEF_ASM(v17)
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DEF_ASM(v18)
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DEF_ASM(v19)
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DEF_ASM(v20)
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DEF_ASM(v21)
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DEF_ASM(v22)
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DEF_ASM(v23)
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DEF_ASM(v24)
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DEF_ASM(v25)
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DEF_ASM(v26)
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DEF_ASM(v27)
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DEF_ASM(v28)
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DEF_ASM(v29)
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DEF_ASM(v30)
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DEF_ASM(v31)
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/* SIMD/FP registers - 64-bit views (double) */
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DEF_ASM(d0)
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DEF_ASM(d1)
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DEF_ASM(d2)
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DEF_ASM(d3)
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DEF_ASM(d4)
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DEF_ASM(d5)
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DEF_ASM(d6)
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DEF_ASM(d7)
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DEF_ASM(d8)
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DEF_ASM(d9)
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DEF_ASM(d10)
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DEF_ASM(d11)
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DEF_ASM(d12)
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DEF_ASM(d13)
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DEF_ASM(d14)
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DEF_ASM(d15)
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DEF_ASM(d16)
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DEF_ASM(d17)
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DEF_ASM(d18)
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DEF_ASM(d19)
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DEF_ASM(d20)
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DEF_ASM(d21)
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DEF_ASM(d22)
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DEF_ASM(d23)
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DEF_ASM(d24)
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DEF_ASM(d25)
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DEF_ASM(d26)
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DEF_ASM(d27)
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DEF_ASM(d28)
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DEF_ASM(d29)
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DEF_ASM(d30)
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DEF_ASM(d31)
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/* SIMD/FP registers - 32-bit views (single) */
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DEF_ASM(s0)
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DEF_ASM(s1)
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DEF_ASM(s2)
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DEF_ASM(s3)
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DEF_ASM(s4)
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DEF_ASM(s5)
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DEF_ASM(s6)
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DEF_ASM(s7)
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DEF_ASM(s8)
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DEF_ASM(s9)
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DEF_ASM(s10)
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DEF_ASM(s11)
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DEF_ASM(s12)
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DEF_ASM(s13)
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DEF_ASM(s14)
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DEF_ASM(s15)
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DEF_ASM(s16)
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DEF_ASM(s17)
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DEF_ASM(s18)
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DEF_ASM(s19)
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DEF_ASM(s20)
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DEF_ASM(s21)
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DEF_ASM(s22)
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DEF_ASM(s23)
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DEF_ASM(s24)
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DEF_ASM(s25)
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DEF_ASM(s26)
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DEF_ASM(s27)
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DEF_ASM(s28)
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DEF_ASM(s29)
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DEF_ASM(s30)
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DEF_ASM(s31)
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/* SIMD/FP registers - 16-bit views (half) */
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DEF_ASM(h0)
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DEF_ASM(h1)
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DEF_ASM(h2)
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DEF_ASM(h3)
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DEF_ASM(h4)
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DEF_ASM(h5)
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DEF_ASM(h6)
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DEF_ASM(h7)
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DEF_ASM(h8)
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DEF_ASM(h9)
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DEF_ASM(h10)
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DEF_ASM(h11)
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DEF_ASM(h12)
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DEF_ASM(h13)
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DEF_ASM(h14)
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DEF_ASM(h15)
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DEF_ASM(h16)
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DEF_ASM(h17)
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DEF_ASM(h18)
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DEF_ASM(h19)
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DEF_ASM(h20)
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DEF_ASM(h21)
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DEF_ASM(h22)
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DEF_ASM(h23)
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DEF_ASM(h24)
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DEF_ASM(h25)
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DEF_ASM(h26)
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DEF_ASM(h27)
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DEF_ASM(h28)
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DEF_ASM(h29)
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DEF_ASM(h30)
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DEF_ASM(h31)
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/* SIMD/FP registers - 8-bit views (byte) */
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DEF_ASM(b0)
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DEF_ASM(b1)
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DEF_ASM(b2)
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DEF_ASM(b3)
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DEF_ASM(b4)
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DEF_ASM(b5)
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DEF_ASM(b6)
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DEF_ASM(b7)
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DEF_ASM(b8)
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DEF_ASM(b9)
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DEF_ASM(b10)
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DEF_ASM(b11)
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DEF_ASM(b12)
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DEF_ASM(b13)
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DEF_ASM(b14)
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DEF_ASM(b15)
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DEF_ASM(b16)
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DEF_ASM(b17)
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DEF_ASM(b18)
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DEF_ASM(b19)
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DEF_ASM(b20)
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DEF_ASM(b21)
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DEF_ASM(b22)
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DEF_ASM(b23)
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DEF_ASM(b24)
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DEF_ASM(b25)
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DEF_ASM(b26)
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DEF_ASM(b27)
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DEF_ASM(b28)
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DEF_ASM(b29)
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DEF_ASM(b30)
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DEF_ASM(b31)
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/* Condition codes */
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DEF_ASM(eq)
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DEF_ASM(ne)
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DEF_ASM(cs)
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DEF_ASM(hs)
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DEF_ASM(cc)
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DEF_ASM(lo)
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DEF_ASM(mi)
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DEF_ASM(pl)
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DEF_ASM(vs)
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DEF_ASM(vc)
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DEF_ASM(hi)
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DEF_ASM(ls)
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DEF_ASM(ge)
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DEF_ASM(lt)
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DEF_ASM(gt)
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DEF_ASM(le)
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DEF_ASM(al)
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/* Data processing - arithmetic (no condition suffixes for ARM64) */
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DEF_ASM(add)
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DEF_ASM(adds)
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DEF_ASM(sub)
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DEF_ASM(subs)
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DEF_ASM(cmn)
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DEF_ASM(cmp)
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DEF_ASM(neg)
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DEF_ASM(negs)
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DEF_ASM(adc)
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DEF_ASM(adcs)
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DEF_ASM(sbc)
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DEF_ASM(sbcs)
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DEF_ASM(ngc)
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DEF_ASM(ngcs)
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/* Data processing - bitwise */
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DEF_ASM(and)
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DEF_ASM(ands)
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DEF_ASM(bic)
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DEF_ASM(bics)
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DEF_ASM(orr)
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DEF_ASM(orn)
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DEF_ASM(eor)
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DEF_ASM(eon)
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DEF_ASM(mvn)
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DEF_ASM(mov)
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/* Shifts */
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DEF_ASM(lsl)
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DEF_ASM(lsr)
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DEF_ASM(asr)
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DEF_ASM(ror)
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/* Multiply/divide */
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DEF_ASM(mul)
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DEF_ASM(madd)
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DEF_ASM(msub)
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DEF_ASM(smaddl)
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DEF_ASM(smsubl)
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DEF_ASM(umaddl)
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DEF_ASM(umsubl)
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DEF_ASM(smulh)
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DEF_ASM(umulh)
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DEF_ASM(udiv)
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DEF_ASM(sdiv)
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/* Moves */
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DEF_ASM(movz)
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DEF_ASM(movn)
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DEF_ASM(movk)
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/* Compare/test */
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DEF_ASM(tst)
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DEF_ASM(teq)
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/* Branch instructions */
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DEF_ASM(b)
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DEF_ASM(bl)
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DEF_ASM(br)
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DEF_ASM(blr)
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DEF_ASM(ret)
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DEF_ASM(cbz)
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DEF_ASM(cbnz)
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DEF_ASM(tbz)
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DEF_ASM(tbnz)
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/* Conditional branches */
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DEF_ASM(beq)
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DEF_ASM(bne)
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DEF_ASM(bcs)
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DEF_ASM(bhs)
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DEF_ASM(bcc)
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DEF_ASM(blo)
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DEF_ASM(bmi)
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DEF_ASM(bpl)
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DEF_ASM(bvs)
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DEF_ASM(bvc)
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DEF_ASM(bhi)
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DEF_ASM(bls)
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DEF_ASM(bge)
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DEF_ASM(blt)
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DEF_ASM(bgt)
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DEF_ASM(ble)
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/* Conditional select */
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DEF_ASM(csel)
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DEF_ASM(csinc)
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DEF_ASM(csinv)
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DEF_ASM(csneg)
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/* Load/Store */
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DEF_ASM(ldr)
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DEF_ASM(ldrb)
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DEF_ASM(ldrh)
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DEF_ASM(ldrsb)
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DEF_ASM(ldrsh)
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DEF_ASM(ldrsw)
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DEF_ASM(str)
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DEF_ASM(strb)
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DEF_ASM(strh)
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/* Load/Store - pair */
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DEF_ASM(ldp)
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DEF_ASM(stp)
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DEF_ASM(ldpsw)
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/* Address generation */
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DEF_ASM(adr)
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DEF_ASM(adrp)
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/* System instructions */
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DEF_ASM(mrs)
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DEF_ASM(msr)
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DEF_ASM(nop)
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DEF_ASM(wfi)
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DEF_ASM(wfe)
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DEF_ASM(sev)
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DEF_ASM(sevl)
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DEF_ASM(isb)
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DEF_ASM(dsb)
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DEF_ASM(dmb)
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/* Hints */
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DEF_ASM(yield)
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DEF_ASM(clrex)
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/* Push/pop */
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DEF_ASM(push)
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DEF_ASM(pop)
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/* Floating point */
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DEF_ASM(fmov)
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DEF_ASM(fadd)
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DEF_ASM(fsub)
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DEF_ASM(fmul)
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DEF_ASM(fnmul)
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DEF_ASM(fdiv)
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DEF_ASM(fmax)
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DEF_ASM(fmin)
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DEF_ASM(fmaxnm)
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DEF_ASM(fminnm)
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DEF_ASM(fsqrt)
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DEF_ASM(fabs)
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DEF_ASM(fneg)
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DEF_ASM(frintn)
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DEF_ASM(frintp)
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DEF_ASM(frintm)
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DEF_ASM(frintz)
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DEF_ASM(frinta)
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DEF_ASM(frintx)
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DEF_ASM(frinti)
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DEF_ASM(fcmp)
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DEF_ASM(fcmpe)
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DEF_ASM(fccmp)
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DEF_ASM(fccmpe)
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DEF_ASM(fcvts)
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DEF_ASM(fcvtd)
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DEF_ASM(fcvth)
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DEF_ASM(fcvtx)
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DEF_ASM(scvtf)
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DEF_ASM(ucvtf)
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DEF_ASM(fcvtns)
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DEF_ASM(fcvtnu)
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DEF_ASM(fcvtps)
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DEF_ASM(fcvtpu)
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/* SIMD instructions */
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DEF_ASM(addv)
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DEF_ASM(faddp)
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DEF_ASM(fmaxp)
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DEF_ASM(fminp)
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DEF_ASM(fmaxnmp)
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DEF_ASM(fminnmp)
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DEF_ASM(addp)
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DEF_ASM(bif)
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DEF_ASM(bit)
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DEF_ASM(bsl)
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DEF_ASM(dup)
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DEF_ASM(ext)
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DEF_ASM(ins)
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DEF_ASM(movi)
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DEF_ASM(mvni)
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DEF_ASM(not)
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DEF_ASM(shl)
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DEF_ASM(shll)
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DEF_ASM(shll2)
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DEF_ASM(sli)
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DEF_ASM(sri)
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DEF_ASM(sqshl)
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DEF_ASM(sqshlu)
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DEF_ASM(srshl)
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DEF_ASM(sshll)
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DEF_ASM(sshll2)
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DEF_ASM(sshr)
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DEF_ASM(ushll)
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DEF_ASM(ushll2)
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DEF_ASM(ushr)
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/* Misc */
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DEF_ASM(bfm)
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DEF_ASM(sbfm)
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DEF_ASM(ubfm)
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DEF_ASM(extr)
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DEF_ASM(crc32b)
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DEF_ASM(crc32h)
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DEF_ASM(crc32w)
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DEF_ASM(crc32x)
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DEF_ASM(crc32cb)
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DEF_ASM(crc32ch)
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DEF_ASM(crc32cw)
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DEF_ASM(crc32cx)
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DEF_ASM(rev)
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DEF_ASM(rev16)
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DEF_ASM(rev32)
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DEF_ASM(rev64)
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DEF_ASM(clz)
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DEF_ASM(cls)
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DEF_ASM(rbit)
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/* Exception generating */
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DEF_ASM(svc)
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DEF_ASM(hvc)
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DEF_ASM(smc)
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DEF_ASM(brk)
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DEF_ASM(hlt)
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DEF_ASM(dcps1)
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DEF_ASM(dcps2)
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DEF_ASM(dcps3)
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/* Conditional branches */
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DEF_ASM(b_eq)
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DEF_ASM(b_ne)
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DEF_ASM(b_cs)
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DEF_ASM(b_cc)
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DEF_ASM(b_mi)
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DEF_ASM(b_pl)
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DEF_ASM(b_vs)
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DEF_ASM(b_vc)
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DEF_ASM(b_hi)
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DEF_ASM(b_ls)
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DEF_ASM(b_ge)
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DEF_ASM(b_lt)
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DEF_ASM(b_gt)
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DEF_ASM(b_le)
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/* LD/ST exclusive */
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DEF_ASM(ldxr)
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DEF_ASM(ldxrb)
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DEF_ASM(ldxrh)
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DEF_ASM(stxr)
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DEF_ASM(stxrb)
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DEF_ASM(stxrh)
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DEF_ASM(ldaxr)
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DEF_ASM(ldaxrb)
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DEF_ASM(ldaxrh)
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DEF_ASM(stlxr)
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DEF_ASM(stlxrb)
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DEF_ASM(stlxrh)
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/* LD/ST acquire-release */
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DEF_ASM(ldar)
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DEF_ASM(ldarb)
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DEF_ASM(ldarh)
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DEF_ASM(stlr)
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DEF_ASM(stlrb)
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DEF_ASM(stlrh)
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DEF_ASM(ldalr)
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DEF_ASM(ldalrb)
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DEF_ASM(ldalrh)
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DEF_ASM(stllr)
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DEF_ASM(stllrb)
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DEF_ASM(stllrh)
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/* LD/ST unscaled immediate */
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DEF_ASM(ldur)
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DEF_ASM(ldurb)
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DEF_ASM(ldurh)
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DEF_ASM(ldursb)
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DEF_ASM(ldursh)
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DEF_ASM(ldursw)
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DEF_ASM(stur)
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DEF_ASM(sturb)
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DEF_ASM(sturh)
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/* Vector load/store */
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DEF_ASM(ld1)
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DEF_ASM(st1)
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DEF_ASM(ld2)
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DEF_ASM(st2)
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DEF_ASM(ld3)
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DEF_ASM(st3)
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DEF_ASM(ld4)
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DEF_ASM(st4)
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/* ------------------------------------------------------------------ */
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/* ARM64 instruction opcode constants and encoding helpers */
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/* ------------------------------------------------------------------ */
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/* Data processing - immediate */
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#define ARM64_ADD_IMM 0x11000000U
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#define ARM64_ADDS_IMM 0x2B000000U
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#define ARM64_SUB_IMM 0x51000000U
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#define ARM64_SUBS_IMM 0x6B000000U
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/* Data processing - register */
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#define ARM64_ADD_REG 0x0B000000U
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#define ARM64_ADDS_REG 0x2B000000U
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#define ARM64_SUB_REG 0x4B000000U
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#define ARM64_SUBS_REG 0x6B000000U
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#define ARM64_AND_REG 0x0A000000U
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#define ARM64_ANDS_REG 0x6A000000U
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#define ARM64_ORR_REG 0x2A000000U
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#define ARM64_EOR_REG 0x4A000000U
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#define ARM64_MUL_REG 0x1B000000U /* Base opcode, Rm/Rn/Rd must be filled in */
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/* Move wide immediate */
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#define ARM64_MOVZ 0x52800000U
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#define ARM64_MOVN 0x12800000U
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#define ARM64_MOVK 0xF2800000U
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/* ARM64_MOVI_W/X removed: MOVI is a SIMD&FP instruction, not general-purpose */
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/* Use MOVZ/MOVN/MOVK for general-purpose, or SIMD MOVI variants (0x0F000400, etc.) */
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/* MOVZ/MOVN 64-bit base opcodes */
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#define ARM64_MOVZ64 0xD2800000U /* MOVZ (64-bit), use with ARM64_HW() */
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#define ARM64_MOVN64 0x92800000U /* MOVN (64-bit), use with ARM64_HW() */
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/* Move wide immediate shift field (LSL #0/16/32/48 encoded as hw*16) */
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#define ARM64_HW(v) (((uint32_t)(v) & 3) << 21)
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/* Load/store register (unsigned immediate) */
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#define ARM64_LDR_X 0xF9400000U
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#define ARM64_LDR_W 0xB9400000U
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#define ARM64_LDR_B 0x39400000U
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#define ARM64_LDR_H 0x79400000U
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#define ARM64_LDR_D 0xFD400000U
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#define ARM64_LDR_S 0xBD400000U
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#define ARM64_STR_X 0xF9000000U
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#define ARM64_STR_W 0xB9000000U
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#define ARM64_STR_B 0x39000000U
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#define ARM64_STR_H 0x79000000U
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#define ARM64_STR_D 0xFD000000U
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#define ARM64_STR_S 0xBD000000U
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/* Load/store register (unscaled immediate) */
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#define ARM64_LDUR_X 0xF8400000U
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#define ARM64_LDUR_W 0xB8400000U
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#define ARM64_LDUR_B 0x38400000U
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#define ARM64_LDUR_H 0x78400000U
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#define ARM64_STUR_X 0xF8000000U
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#define ARM64_STUR_W 0xB8000000U
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#define ARM64_STUR_B 0x38000000U
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#define ARM64_STUR_H 0x78000000U
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/* Load/store register (register offset) */
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#define ARM64_LDR_X_REG 0xF8606800U
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#define ARM64_LDR_W_REG 0xB8606800U
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#define ARM64_LDR_B_REG 0x38606800U
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#define ARM64_LDR_H_REG 0x78606800U
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#define ARM64_STR_X_REG 0xF8206800U
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#define ARM64_STR_W_REG 0xB8206800U
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#define ARM64_STR_B_REG 0x38206800U
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#define ARM64_STR_H_REG 0x78206800U
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/* Load/store (pre/post-indexed) */
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#define ARM64_STR_X_PRE 0xF8000000U /* STR X pre-indexed base */
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#define ARM64_LDR_X_POST 0xF8400000U /* LDR X post-indexed base */
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/* SIMD load/store (unsigned immediate) */
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#define ARM64_LDR_SCALAR 0x3D400000U /* Base for scalar load (size built dynamically) */
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#define ARM64_LDR_S_VEC 0xBD400000U
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#define ARM64_LDR_D_VEC 0xFD400000U
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#define ARM64_LDR_Q_VEC 0x3DC00000U
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#define ARM64_STR_SCALAR 0x3D000000U /* Base for scalar store (size built dynamically) */
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#define ARM64_STR_S_VEC 0xBD000000U
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#define ARM64_STR_D_VEC 0xFD000000U
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#define ARM64_STR_Q_VEC 0x3D800000U
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/* SIMD load/store (unscaled immediate) */
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#define ARM64_LDUR_S_SIMD 0xBC400000U
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#define ARM64_LDUR_D_SIMD 0xFC400000U
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#define ARM64_LDUR_Q_SIMD 0x3C400000U
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#define ARM64_STUR_S_SIMD 0xBC000000U
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#define ARM64_STUR_D_SIMD 0xFC000000U
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#define ARM64_STUR_Q_SIMD 0x3C000000U
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/* SIMD load/store (register offset) */
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#define ARM64_LDR_S_REG 0xBC606800U
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#define ARM64_LDR_D_REG 0xFC606800U
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#define ARM64_LDR_Q_REG 0x3C606800U
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#define ARM64_STR_S_REG 0xBC206800U
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#define ARM64_STR_D_REG 0xFC206800U
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#define ARM64_STR_Q_REG 0x3C206800U
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/* Load/store pair */
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#define ARM64_LDP_X 0xA9400000U
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#define ARM64_LDP_X_PRE 0xA9C00000U
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#define ARM64_LDP_X_POST 0xA8C00000U
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#define ARM64_STP_X 0xA9000000U
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#define ARM64_STP_X_PRE 0xA9800000U
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#define ARM64_STP_X_POST 0xA8800000U
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#define ARM64_LDP_D 0x6D400000U
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#define ARM64_LDP_D_PRE 0x6DC00000U
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#define ARM64_LDP_D_POST 0x6CC00000U
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#define ARM64_STP_D 0x6D000000U
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#define ARM64_STP_D_PRE 0x6D800000U
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#define ARM64_STP_D_POST 0x6C800000U
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/* Branch instructions */
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#define ARM64_B 0x14000000U
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#define ARM64_BL 0x94000000U
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#define ARM64_BR 0xD61F0000U
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#define ARM64_BLR 0xD63F0000U
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#define ARM64_RET 0xD65F0000U
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/* Conditional branch */
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#define ARM64_B_COND 0x54000000U
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/* Compare and branch */
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#define ARM64_CBZ 0x34000000U
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#define ARM64_CBNZ 0x35000000U
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/* System instructions */
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#define ARM64_NOP 0xD503201FU
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#define ARM64_ISB 0xD50330DFU
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#define ARM64_DSB 0xD503309FU
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#define ARM64_DMB 0xD50330BFU
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#define ARM64_MRS 0xD5380000U
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#define ARM64_MSR 0xD5180000U
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#define ARM64_MRS_FPCR 0xD53B4400U
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#define ARM64_MRS_FPSR 0xD53B4420U
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#define ARM64_MSR_FPCR 0xD51B4400U
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#define ARM64_MSR_FPSR 0xD51B4420U
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/* Shifts (register) */
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#define ARM64_LSL_REG 0x1AC02000U
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#define ARM64_LSR_REG 0x1AC02400U
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#define ARM64_ASR_REG 0x1AC02800U
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#define ARM64_ROR_REG 0x1AC02C00U
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/* Shifts (immediate - UBFM/SBFM) */
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#define ARM64_LSL_IMM 0xD3400000U
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#define ARM64_LSR_IMM 0xD3400000U
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#define ARM64_LSR_IMM_32 0x53000000U /* 32-bit LSR base */
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#define ARM64_ASR_IMM 0x93400000U
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/* Shifted register encoding for ORR/AND/EOR */
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#define ARM64_SHIFT_LSL(imm) (((uint32_t)(imm) & 63) << 10)
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#define ARM64_SHIFT_LSR(imm) (0x00200000U | (((uint32_t)(imm) & 63) << 10))
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#define ARM64_SHIFT_ASR(imm) (0x00400000U | (((uint32_t)(imm) & 63) << 10))
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#define ARM64_SHIFT_ROR(imm) (0x00600000U | (((uint32_t)(imm) & 63) << 10))
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/* UBFM/SBFM immediate fields (for LSL/LSR/ASR immediate aliases) */
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#define ARM64_IMM_R(r) (((uint32_t)(r) & 0x3F) << 16)
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#define ARM64_IMM_S(s) (((uint32_t)(s) & 0x3F) << 10)
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|
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/* Extended register encoding */
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#define ARM64_EXTEND_LSL(lsl) (((uint32_t)(lsl) & 7) << 10)
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/* MOV (register) - ORR with zero register */
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#define ARM64_MOV_REG 0x2A0003E0U
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|
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/* Address generation */
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#define ARM64_ADRP 0x90000000U
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#define ARM64_ADR 0x10000000U
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/* Logical immediate */
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#define ARM64_AND_IMM 0x12000000U
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#define ARM64_ORR_IMM_BASE 0x32000000U
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#define ARM64_EOR_IMM 0x52000000U
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#define ARM64_ANDS_IMM 0x72000000U
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#define ARM64_ORR_IMM 0x320003E0U /* ORR immediate alias with Rn = XZR/WZR */
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|
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/* ------------------------------------------------------------------ */
|
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/* ARM64 instruction encoding helper macros */
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|
/* ------------------------------------------------------------------ */
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|
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/* Register field encodings */
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#define ARM64_RD(r) ((uint32_t)(r) & 0x1FU)
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#define ARM64_RN(r) (((uint32_t)(r) & 0x1FU) << 5)
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#define ARM64_RM(r) (((uint32_t)(r) & 0x1FU) << 16)
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#define ARM64_RT(r) ((uint32_t)(r) & 0x1FU)
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#define ARM64_RT2(r) (((uint32_t)(r) & 0x1FU) << 10)
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|
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/* Immediate field encodings */
|
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#define ARM64_IMM12(v) (((uint32_t)(v) & 0xFFFU) << 10)
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#define ARM64_IMM7(v) (((uint32_t)(v) & 0x7FU) << 15)
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#define ARM64_IMM14(v) (((uint32_t)(v) & 0x3FFFU) << 5)
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#define ARM64_IMM16(v) (((uint32_t)(v) & 0xFFFFU) << 5)
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#define ARM64_IMM_HW(v, hw) (((uint32_t)(v) & 0xFFFFU) << 5 | (((hw) & 3) << 21))
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|
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/* Shift and size encodings */
|
|
#define ARM64_SIZE(s) (((uint32_t)(s) & 3) << 30)
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#define ARM64_SF(s) (((uint32_t)(s) & 1) << 31)
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#define ARM64_S(v) (((uint32_t)(v) & 1) << 29)
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#define ARM64_N(v) (((uint32_t)(v) & 1) << 22)
|
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#define ARM64_SH(v) (((uint32_t)(v) & 1) << 22)
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|
|
/* Condition code encoding */
|
|
#define ARM64_COND(c) ((uint32_t)(c) & 0xFU)
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|
|
|
/* Branch offset encoding */
|
|
#define ARM64_OFFSET26(v) (((uint32_t)(v) >> 2) & 0x3FFFFFFU)
|
|
#define ARM64_OFFSET19(v) (((uint32_t)(v) >> 2) & 0x7FFFFU)
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|
#define ARM64_OFFSET14(v) (((uint32_t)(v) >> 2) & 0x3FFFU)
|
|
|
|
/* Special register field (for MRS/MSR) */
|
|
#undef ARM64_SYSREG
|
|
#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
|
|
((((op0) & 3) << 19) | (((op1) & 7) << 16) | \
|
|
(((crn) & 15) << 12) | (((crm) & 15) << 8) | (((op2) & 7) << 5))
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|
|
|
/* Barrier option encoding */
|
|
#define ARM64_ISB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8)
|
|
#define ARM64_DSB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8)
|
|
#define ARM64_DMB_OPTION(opt) (((uint32_t)(opt) & 0xFU) << 8)
|
|
|
|
/* Additional opcodes for code generator - VERIFIED */
|
|
/* Note: Many of these are specific instances, not general templates */
|
|
|
|
/* Floating-point move - VERIFIED */
|
|
#define ARM64_FMOV_D_S 0x1E604000U /* FMOV Dd,Dn (scalar) */
|
|
#define ARM64_FMOV_X_D 0x9E660000U /* FMOV Xd,Dn (general to FP) */
|
|
#define ARM64_FMOV_W_S 0x1E260000U /* FMOV Wd,Sn (general to FP) */
|
|
/* ARM64_FMOV_S_D removed: 0x4EA01C00 is SIMD vector, not scalar FMOV */
|
|
/* Use 0x1E204000 for FMOV Sd,Sn or 0x1E604000 variant for cross-size */
|
|
|
|
/* FMOV variants for code generator */
|
|
#define ARM64_FMOV_SCALAR 0x1E604000U /* FMOV Dd, Dn (scalar FP) */
|
|
#define ARM64_FMOV_XD 0x9E660000U /* FMOV Xd, Dn (FP to GP 64-bit) */
|
|
#define ARM64_FMOV_WS 0x1E260000U /* FMOV Wd, Sn (FP to GP 32-bit) */
|
|
|
|
/* MOV vector (ORR vector register alias) */
|
|
#define ARM64_MOV_V16B 0x4EA01C00U /* MOV Vd.16B, Vn.16B (ORR vector, Rm=Rn alias) */
|
|
|
|
/* Load/Store SIMD&FP - Base opcodes (register fields must be filled in) */
|
|
#define ARM64_STR_Q_PRE 0x3C800000U /* STR Q pre-index base */
|
|
#define ARM64_LDR_Q_POST 0x3CC00000U /* LDR Q post-index base */
|
|
|
|
/* LDPSW - Base opcode (register fields must be filled in) */
|
|
/* Use gen_ldst_pair() with appropriate mode for LDPSW */
|
|
/* Base encodings: 0x68C00000 (post), 0x69400000 (offset), 0x69C00000 (pre) */
|
|
|
|
/* ARM64_LDR_S_SIMD removed: 0x0D00801C is not a standard encoding */
|
|
/* Use ARM64_LDR_S (0xBD400000) for scalar S or ARM64_LDR_S_VEC for SIMD */
|
|
|
|
/* MOV between SIMD and general - Use UMOV/SMOV instead */
|
|
/* ARM64_MOV_V_D removed: 0x4E083C00 is UMOV/SMOV encoding */
|
|
/* Use appropriate UMOV/SMOV base: 0x0E002C00/0x0E003C00 (32-bit) */
|
|
/* or 0x4E002C00/0x4E003C00 (64-bit) */
|
|
|
|
/* Verified from previous section */
|
|
#define ARM64_FCMP 0x1E202008U /* FCMP with zero */
|
|
#define ARM64_SDIV 0x1AC00C00U /* SDIV (32-bit) */
|
|
|
|
/* EXTR (Extract) */
|
|
#define ARM64_EXTR 0x13800000U /* EXTR Wd, Wn, Wm, #imm (32-bit) */
|
|
#define ARM64_EXTR64 0x93C00000U /* EXTR Xd, Xn, Xm, #imm (64-bit) */
|
|
|
|
/* ARM64_MUL removed - use ARM64_MUL_REG with gen_dp_reg() */
|
|
|
|
/* ORR shifted - Base opcodes (register fields must be filled in) */
|
|
#define ARM64_ORR_REG_LSL 0x2A000000U /* ORR (shifted register) base */
|
|
/* ARM64_ORR_REG_LSL32 removed: use ARM64_ORR_REG_LSL with SF=1 */
|
|
/* ARM64_ORR_REG_MOV is duplicate of ARM64_MOV_REG */
|
|
|
|
/* LSR immediate - These are UBFM encodings, use gen_shift() instead */
|
|
/* Base UBFM encodings: 0x53000000 (W), 0xD3400000 (X) */
|
|
/* gen_shift() handles immr/imms encoding for LSR/LSL/ASR */
|
|
/* ARM64_LSR_W_8, ARM64_LSR_X_8, ARM64_LSR_X_16, ARM64_LSR_X_24 removed */
|
|
/* They are specific instances, not templates */
|
|
|
|
/* SUB shifted - Base opcode (use gen_sub_reg or asm handler) */
|
|
#define ARM64_SUB_REG_LSL 0xCB000000U /* SUB (shifted register) base */
|
|
|
|
/* Duplicates removed: ARM64_LDP_X, ARM64_B, ARM64_BL, ARM64_BR, ARM64_NOP */
|
|
/* These are already defined in their respective sections above */
|