Add handlers for csrr, csrw, csrwi, csrsi, csrci as pseudo-instructions:
csrr rd, csr -> csrrs rd, csr, x0
csrw csr, rs -> csrrw x0, csr, rs
csrwi csr, uimm -> csrrwi x0, csr, uimm
csrsi csr, uimm -> csrrsi x0, csr, uimm
csrci csr, uimm -> csrrci x0, csr, uimm
Tokens were already defined in riscv64-tok.h. Tested on
Spacemit X100 using fcsr (0x003) which is accessible in user mode.
cycle/instret CSRs are privileged and not accessible from Linux
user mode on this hardware.
Adds the 8 most essential floating-point arithmetic instructions:
fadd.s/d, fsub.s/d, fmul.s/d, fdiv.s/d, for both single and double
precision. These complement the existing fsgnj/fmax/fmin/fsqrt set.
Comparison (feq/flt/fle) and conversion (fcvt) instructions remain
as future work.
sext.w: addiw rd, rs, 0 (sign-extend 32-bit word)
fmv.s/fmv.d: fsgnj.s/d rd, rs, rs (float register move)
fneg.s/fneg.d: fsgnjn.s/d rd, rs, rs (float register negate)
These were defined in riscv64-tok.h but had no handler code.
CSR pseudo-instructions (csrr, csrw, csrci, csrsi, csrwi) skipped
for now — they require CSR operand parsing in binary mode.
For branch targets that are external/static symbols (where the
offset cannot be determined at assembly time), expand to:
b<inverse> .+8 # skip if condition false
auipc t0, %pcrel_hi # load target upper bits
jalr x0, %pcrel_lo(t0) # jump
This handles the ±4 KiB B-type limitation without requiring
linker relaxation (R_RISCV_RELAX). Local immediates within
range still use the compact B-type encoding.
On RV64, long long (64-bit) fits in a single general-purpose register.
The existing load/store calls already handle 64-bit values correctly.
The 'not implemented' errors were vestigial from 32-bit architectures
where long long requires a register pair.
Removing these errors allows inline asm to accept 64-bit integer operands
on RV64, which is important since this is the native register width.
neg/negw were incorrectly using asm_emit_i (I-type/xori) with an
immediate of 1, producing 'xori rd, rs, 1' instead of the intended
'sub rd, x0, rs'. Fixed to use asm_emit_r (R-type) with proper
SUB/SUBW opcode (0x33/0x3B, func3=0, func7=0x20).
The old code generated wrong machine code for these pseudo-instructions.
negw now also correctly uses OP-32 (0x3B) for 32-bit subtraction.
workflow:
- revert 'pinact for security' for readability
from 831c3fa184
tccpp.c:
- remove code that allows tcc to parse numbers incorrectly (*)
from 829c848520
tccgen.c:
- Revert "Relaxed the 'incompatible pointer type' warning a bit" (*)
from d9ec17d334.
tccrun.c:
- remove support for -nostdlib -run
for simplicity, we require "main" with tcc -run always
tccpp.c:
- Revert "Free all preprocessor memmory in case of error."
from c96f0cad61
Remove TinyAlloc->limit instead. Thus it can do also bigger
allocs. Big TokenStrings (like 200kb+ when compiling tcc)
may come from inline functions or from large initializers.
Makefile/configure:
- use --config-pie for configuring tcc output only
- use -fPIC with clang-x86_64 to avoid 32-bit relocs
libtcc.c:
- fix "tcc file.c -run" i.e. -run as last argument
i386-gen.c:
- PIC refactor
(*) sorry, but code in tcc should have a minimum of generic relevance
Put former NATIVE_DEFINES into config.h. Such tcc can be run
and tested directly from source more easily, like for example:
tcc -run tcc.c -B. -run test.c
Also:
- tccelf.c: cleanup
- tccpp.c: avoid stupid clang warning
- configure: reduce -Wno- switches
- tcc.h: inline wait/post_sem()
- tccpe.c: simplify import (assume STT_NOTYPE is function)
This commit fixes the case where the register of for the Extended Asm
input or output is known. Before this commit, the following case:
register long __a0 asm ("a0") = one;
asm volatile (
"ecall\n\t"
: "+r" (__a0) // NOTE the +r here
);
Didn't treat `a0` as an input+output register (+ contraint) as the code
skipped the constraint processing when the register was already chosen
(instead of allocated later).
This issue comes from f081acbfba, that was
taken as a reference in every other Extended Assembler implementation.
NOTE: In order to be able to deal with general-purpose vs floating-point
registers, this commit adds a flag in the 6th bit of the register. If
set, it means the register is a floating-point one. This affects all the
assembler.
Before:
ld rd, rs, imm
sd rs1, rs2, imm
Now:
ld rd, imm(rs)
sd rs2, imm(rs1)
NOTES: Just as in GAS:
- In stores the register order is swapped
- imm is optional
- when imm is not included parenthesis can be removed
add nop
fix asm_emit_i immediate check (negative offsets were missing)
fix check for IM12S
remove non-existent instructions (example: slli64 is just slli with imm=0)
defined tokens for C, M, Ziscr extensions.
separate the base RV32 instructions from the RV64, for potential future
re-use in a RV32-only assembler, from which the RV64-tok can #include
scall, sbreak have been renamed (page 7 of spec),
necessitating some renaming in riscv64-asm.c
riscv-spec-20191213.pdf was used,
in which the "V" extension is not yet ratified.
available under https://riscv.org/technical/specifications/
Tables 16.5–16.7 do not list any "scall"
neither does the privileged spec
3 additional tokens not present in the tables were removed
note that this riscv64-asm.c still contains defects, which will
be addressed in another commit
