Meng Zhuo
7f764f340f
riscv64-asm: complete AMO aq/rl suffixes for all ops
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Add 48 tokens + handlers + dispatch cases for all AMO aq/rl
variants (amoswap, amoand, amoor, amoxor, amomax, amomaxu,
amomin, amominu; each x {.w,.d} x {.aq,.rl,.aqrl}).
GNU-compatible 2-dot naming via DEF_ASM_WITH_SUFFIXES.
Correct funct5 values: amoswap=0x01, amoand=0x0C, amoor=0x08,
amoxor=0x04, amomax=0x14, amomaxu=0x1C, amomin=0x10, amominu=0x18.
Extend 141_riscv_asm amo_main() with 10 representative aq/rl
variants covering all ops x ordering suffix combinations.
Verified against riscv64-linux-gnu-as 2.44.
2026-05-07 11:44:46 +08:00
Meng Zhuo
016087c954
riscv64-asm: implement AMO, fcvt rounding, and fcvt encoding fixes
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AMO (A-extension):
18 base instructions: amoadd/swap/and/or/xor/max/maxu/min/minu .w/.d
6 aq/rl suffixes: amoadd.w.aq/.rl/.aqrl, amoadd.d.aq/.rl/.aqrl
Correct funct5 (GNU as verified):
amoadd=0x00 amoswap=0x01 amoxor=0x04
amoand=0x0C amoor=0x08 amomax=0x14
amomaxu=0x1C amomin=0x10 amominu=0x18
R-type opcode 0x2F, aq/rl in bits [26:25]
FCVT rounding modes (GNU operand syntax):
fcvt.w.s rd, rs1 [, rtz/rne/rup] -- optional 3rd operand
asm_fcvt_opcode() handler with asm_fcvt_rm() helper
Keywords rne=0, rtz=1, rdn=2, rup=3, rmm=4
FCVT encoding fixes:
fcvt.s.d: funct7 0x40->0x20
fcvt.d.s: funct7 0x42->0x21
Tests: 144 CSR, 145 F/D cmp+cvt, 146 AMO, 147 fcvt round.
All verified against riscv64-linux-gnu-as 2.44 on Spacemit X100.
2026-05-06 19:18:17 +08:00
Meng Zhuo
3935c3bb55
riscv64-asm: add basic F/D extension instructions (fadd/fsub/fmul/fdiv)
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Adds the 8 most essential floating-point arithmetic instructions:
fadd.s/d, fsub.s/d, fmul.s/d, fdiv.s/d, for both single and double
precision. These complement the existing fsgnj/fmax/fmin/fsqrt set.
Comparison (feq/flt/fle) and conversion (fcvt) instructions remain
as future work.
2026-05-06 12:30:34 +08:00
Aleksi Hannula
06e24e7eed
Implement some RV64F/D instructions
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This patch implements some instructions required by musl 1.1.24.
2025-11-28 15:23:07 +02:00
noneofyourbusiness
3415dec979
riscv64-tok.h: don't export internal macros
2024-08-11 00:41:21 +02:00
Ekaitz Zarraga
671d03f944
riscv: Add full fence instruction support
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This commit adds support for `fence`'s predecessor and successor
arguments.
2024-04-23 15:10:08 +02:00
Ekaitz Zarraga
c994068175
riscv: asm: Add load-reserved and store-conditional
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Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit
versions.
2024-04-23 12:05:05 +02:00
Ekaitz Zarraga
cbe70fa629
riscv: Add .option assembly directive (unimp)
2024-03-21 13:33:27 +01:00
Ekaitz Zarraga
8bfef6ab18
riscv: Add pseudoinstructions
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call, tail, jump, jr, mv, not, neg, negw, seqz, snez, sltz, sgtz, bnez,
beqz, blez, bgez, bltz, bgtz, li
2024-03-21 13:33:25 +01:00
noneofyourbusiness
ada17a08eb
riscv64-asm.c: add support for calculating addresses of symbols
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add some pseudoinstructions
riscv64-tok.h: add pseudoinstructions from tables 25.{2,3}
2023-12-12 09:44:37 +01:00
noneofyourbusiness
5dc241fee1
riscv64-tok.h: add Zicsr pseudoinstructions, registers
2023-12-10 15:22:41 +01:00
noneofyourbusiness
d87801bd50
riscv64-asm.c: implement C extension
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add nop
fix asm_emit_i immediate check (negative offsets were missing)
fix check for IM12S
remove non-existent instructions (example: slli64 is just slli with imm=0)
2023-12-08 17:07:06 +01:00
noneofyourbusiness
e70fec871b
riscv64-tok.h: update with more instructions from the spec
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defined tokens for C, M, Ziscr extensions.
separate the base RV32 instructions from the RV64, for potential future
re-use in a RV32-only assembler, from which the RV64-tok can #include
scall, sbreak have been renamed (page 7 of spec),
necessitating some renaming in riscv64-asm.c
riscv-spec-20191213.pdf was used,
in which the "V" extension is not yet ratified.
available under https://riscv.org/technical/specifications/
Tables 16.5–16.7 do not list any "scall"
neither does the privileged spec
3 additional tokens not present in the tables were removed
note that this riscv64-asm.c still contains defects, which will
be addressed in another commit
2023-08-10 14:25:03 +02:00
herman ten brugge
cd627c6c40
Fix riscv assembler
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riscv64-asm.c:
asm_opcode: add return
asm_parse_regvar: add abi register names
riscv64-tok.h:
add abi register names
2022-06-07 20:53:14 +02:00
Danny Milosavljevic
b28bf50d2b
riscv64-asm: Add beq, bne, blt, bge, bltu, bgeu
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
9c0760a4d4
riscv64-asm: Add lb, lh, lw, lbu, lhu, ld, lwu, sb, sh, sw, sd
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
1e37ec4917
riscv64-asm: Add add, addi, sub, addw, addd, addiw, addid, subw, subd, xor, xori, or, ori, and, andi, slt, slti, sltu, sltiu
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
8b1a89fbdf
riscv64-asm: Add sll, slli, srl, srli, sra, srai, sllw, slld, slliw, sllid, srlw, srld, srliw, srlid, sraw, srad, sraiw, sraid
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
0b1cc489e1
riscv64-asm: Add lui, auipc
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
e5a898e510
riscv64-asm: Add rdcycle, rdcycleh, rdtime, rdtimeh, rdinstret, rdinstreth
2021-04-23 20:23:45 +02:00
Danny Milosavljevic
4891ab71a0
riscv64-asm: Add fence, fence.i, scall, sbreak, ecall, ebreak, wfi
2021-04-23 20:23:45 +02:00
